SX1261/2 Datasheet Reference (Driver Development Extract)

Source: Semtech SX1261/2 Data Sheet, Rev 2.2, DS.SX1261-2.W.APP, December 2024.

This document extracts the sections relevant for SX1262 LoRa driver development. For the complete datasheet, see semtech.com.

8. Digital Interface and Control

The SX1261/2 is controlled via a serial SPI interface and a set of general purpose input/output (DIOs). At least one DIO must be used for IRQ and the BUSY line is mandatory. BUSY indicates that the chip is ready for new command only if this signal is low.

8.1 Reset

A complete “factory reset” can be issued by toggling pin NRESET. It is automatically followed by the standard calibration procedure and any previous context is lost. The pin should be held low for typically 100us for the Reset to happen.

8.2 SPI Interface

The SPI interface uses a synchronous full-duplex protocol: CPOL = 0, CPHA = 0 (Mode 0). Only the slave side is implemented.

• MOSI is generated by the master on the falling edge of SCK and is sampled by the slave on the rising edge of SCK.
• MISO is generated by the slave on the falling edge of SCK.
• A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.
• SPI runs on the external SCK clock to allow high speed up to 16 MHz.

SPI Timing Requirements (Table 8-1)

8.2.2 SPI Timing When Leaving Sleep Mode

One way for the chip to leave Sleep mode is to wait for a falling edge of NSS. The delay between the falling edge of NSS and the first rising edge of SCK must take into account the wake-up sequence and the chip initialization. During Sleep mode and the initialization phase, BUSY is set high. Once the chip is in STDBY_RC mode, BUSY goes low and the host can start sending a command. This is also true for startup at battery insertion or after a hard reset.

8.3.1 BUSY Control Line

The BUSY control line indicates the status of the internal state machine. When BUSY is held low, the internal state machine is in idle mode and the radio is ready for a command.

For all “write” commands, BUSY is asserted high after time T_SW. T_SW from NSS rising edge to BUSY rising edge is max 600 ns in all cases.

“Read” commands are handled directly without the internal state machine and BUSY remains low after a read command.

Switching Times (Table 8-2)

8.4 Digital Interface Status versus Chip Modes (Table 8-3)

PU = pull up 50kOhm, PD = pull down 50kOhm, HIZ = high impedance, OUT = output, IN = input.

During Reset, Start-up, and Sleep: MISO is High-Impedance. Any SPI read during these states returns undefined data.

8.5 IRQ Handling (Table 8-4)

Note: If DIO2 or DIO3 are used to control the RF Switch or the TCXO, the IRQ is not generated even if it is mapped to the pins.

9. Operational Modes

Operating Modes (Table 9-1)

9.1 Startup

At power-up or after a reset, the chip goes into STARTUP state. The BUSY pin is set to high. When the digital voltage and RC clock become available, the chip can boot up and the CPU takes control. At this stage the BUSY line goes down and the device is ready to accept commands.

9.2 Calibration

The calibration procedure is automatically called in case of POR. Blocks calibrated: RC64k, RC13M, PLL, RX ADC, Image. Once calibration is finished, the chip enters STDBY_RC mode.

9.2.1 Image Calibration for Specific Frequency Bands (Table 9-2)

By default, the image calibration is made in the 902-928 MHz band. When using a TCXO, the calibration fails and the user should request a complete calibration after calling SetDIO3AsTcxoCtrl(...).

9.7 Transmit (TX) Mode

In TX mode, after enabling and ramping-up the Power Amplifier (PA), the contents of the data buffer are transmitted. The timeout can be used as a security to ensure that if the TxDone IRQ is never triggered, the TxTimeout prevents waiting indefinitely. In TX mode, BUSY goes low as soon as the PA has ramped-up and transmission of preamble starts.

10. Host Controller Interface

10.1 Command Structure (Table 10-1)

During byte 0 (the opcode byte), MISO returns RFU (Reserved for Future Use) – NOT the status byte. The status byte appears starting at byte 1.

10.2 Transaction Termination

The host terminates an SPI transaction with the rising NSS signal. The host must not raise NSS within the bytes of a transaction. All parameters must be sent before raising NSS.

11. List of Commands

11.1 Operational Mode Commands (Table 11-1)

11.2 Register and Buffer Access Commands (Table 11-2)

11.3 DIO and IRQ Control (Table 11-3)

11.4 RF, Modulation and Packet Commands (Table 11-4)

13. Command Details (Selected)

13.1.2 SetStandby

StdbyConfig: 0 = STDBY_RC, 1 = STDBY_XOSC.

13.1.4 SetTx

• Starting from STDBY_RC mode, the oscillator is switched ON followed by PLL, then the PA ramps up.
• When the last bit has been sent, an IRQ TX_DONE is generated, the PA ramps down, and the chip goes back to STDBY_RC mode.
• A TIMEOUT IRQ is triggered if TX_DONE is not generated within the timeout period.
• Timeout duration = Timeout * 15.625us
• Timeout = 0x000000: No timeout, device stays in TX until packet is transmitted and returns to STBY_RC.

13.1.5 SetRx

13.1.11 SetRegulatorMode

regModeParam: 0 = Only LDO, 1 = DC_DC+LDO (used for STBY_XOSC, FS, RX and TX modes).

13.1.12 Calibrate Function

calibParam is a bitmask: Bit 0=RC64k, 1=RC13M, 2=PLL, 3=ADC pulse, 4=ADC bulk N, 5=ADC bulk P, 6=Image. 0x7F = calibrate all. Total calibration time ~3.5ms. BUSY is high during calibration.

13.1.14 SetPaConfig

• deviceSel: 0 = SX1262, 1 = SX1261
• paLut: reserved, always 0x01
• For SX1262, paDutyCycle should not be higher than 0x04.

PA Optimal Settings (Table 13-21)

13.1.15 SetRxTxFallbackMode

13.2.1 WriteRegister

13.2.2 ReadRegister

Note: The host must send an NOP after the 2 bytes of address to start receiving data bytes on the next NOP sent.

13.2.3 WriteBuffer

13.2.4 ReadBuffer

Note: An NOP must be sent after sending the offset.

13.3.1 SetDioIrqParams

The interrupt causes a DIO to be set if the corresponding bit in DioxMask AND IrqMask are both set. For example, to route TxDone to DIO1: set bit 0 of both IrqMask and DIO1Mask.

13.3.3 GetIrqStatus

13.3.4 ClearIrqStatus

13.3.5 SetDIO2AsRfSwitchCtrl

enable=1: DIO2 controls RF switch. DIO2=1 during TX, DIO2=0 otherwise.

13.3.6 SetDIO3AsTcxoCtrl

tcxoVoltage (Table 13-35)

Delay duration = delay[23:0] * 15.625us

The XOSC_START_ERR flag is raised at POR or wake-up from Sleep in cold-start condition when TCXO is used. This is expected and should be cleared with ClearDeviceErrors.

Note: The user should take the delay period into account when going into Tx or Rx mode from STDBY_RC mode, since the time needed to switch modes increases with the duration of delay.

13.4.1 SetRfFrequency

RF_frequency = RF_Freq * F_XTAL / 2^25, where F_XTAL = 32 MHz.

To compute RF_Freq from Hz: RF_Freq = freq_hz * 2^25 / 32_000_000

13.4.4 SetTxParams

power: -9 to +22 dBm (encoded as 0xF7 to 0x16) for high power PA (SX1262).

13.4.5 SetModulationParams (LoRa)

• ModParam1 = SF (Spreading Factor)
• ModParam2 = BW (Bandwidth)
• ModParam3 = CR (Coding Rate)
• ModParam4 = LdOpt (Low Data Rate Optimization)

13.5.1 GetStatus

Status Byte Format (Table 13-76)

Chip mode:

Command status:

13.5.2 GetRxBufferStatus

13.5.3 GetPacketStatus (LoRa)

• Actual signal power = -RssiPkt/2 (dBm)
• Actual SNR = SnrPkt/4 (dB)

15. Known Limitations

15.1 Modulation Quality with 500kHz LoRa Bandwidth

Before any packet transmission, bit #2 at register address 0x0889 shall be set to:

• 0 if the LoRa BW = 500kHz
• 1 for any other LoRa BW or (G)FSK configuration

Must be applied before each packet transmission.

15.2 Better Resistance to Antenna Mismatch (TX PA Clamp)

During chip initialization on the SX1262, the register TxClampConfig at address 0x08D8 should be modified. Bits 4-1 must be set to “1111” (default value “0100”).

value = ReadRegister(0x08D8)
value = value | 0x1E
WriteRegister(value, 0x08D8)

Must be done after POR or wake-up from cold start.

15.3 Implicit Header Mode Timeout Behavior

After ANY Rx with Timeout active sequence, stop the RTC and clear the timeout event:

WriteRegister(0x00, 0x0920)
value = ReadRegister(0x0944)
value = value | 0x02
WriteRegister(value, 0x0944)

15.4 Optimizing the Inverted IQ Operation

Bit 2 at address 0x0736 must be set to:

• “0” when using inverted IQ polarity
• “1” when using standard IQ polarity

Key Register Addresses

Init Sequence Summary (from Semtech reference driver + RNode)

1. Hardware reset (NRESET LOW 100us, HIGH, wait BUSY LOW)
2. SetStandby(STBY_RC) [0x80, 0x00]
3. SetRegulatorMode(DC_DC) [0x96, 0x01]
4. SetDIO2AsRfSwitchCtrl(enable) [0x9D, 0x01]
5. ClearDeviceErrors [0x07, 0x00, 0x00]
6. SetDIO3AsTcxoCtrl(1.8V, timeout) [0x97, 0x02, t2, t1, t0]
7. Calibrate(all) [0x89, 0x7F] — wait BUSY LOW (~3.5ms)
8. CalibrateImage(863-870MHz) [0x98, 0xD7, 0xDB]
9. SetPacketType(LoRa) [0x8A, 0x01]
10. SetRfFrequency(freq) [0x86, f3, f2, f1, f0]
11. SetPaConfig(0x04, 0x07, 0x00, 0x01) for +22dBm SX1262
12. SetTxParams(power, ramp) [0x8E, pwr, ramp]
13. SetBufferBaseAddress(0, 0) [0x8F, 0x00, 0x00]
14. SetModulationParams(SF, BW, CR, LDRO) [0x8B, sf, bw, cr, ldro, 0,0,0,0]
15. SetPacketParams(preamble, header, len, crc, iq) [0x8C, ...]
16. Write LoRa sync word to register 0x0740
17. Apply workarounds: TxClamp (0x08D8), BW500 (0x0889), IQ (0x0736)
18. Set RxGain to 0x96 (boosted) at register 0x08AC

TX Sequence

1. SetDioIrqParams(TxDone|Timeout on DIO1) [0x08, mask_hi, mask_lo, dio1_hi, dio1_lo, 0,0, 0,0]
2. ClearIrqStatus(all) [0x02, 0xFF, 0xFF]
3. WriteBuffer(0, payload) [0x0E, 0x00, data...]
4. SetTx(timeout) [0x83, t2, t1, t0] — timeout=0 for no timeout
5. Wait for DIO1 HIGH (TxDone IRQ)
6. ClearIrqStatus(TxDone) [0x02, 0x00, 0x01]

RX Sequence

1. SetDioIrqParams(RxDone|Timeout|CrcErr on DIO1)
2. ClearIrqStatus(all) [0x02, 0xFF, 0xFF]
3. SetRx(timeout) [0x82, t2, t1, t0]
4. Wait for DIO1 HIGH
5. GetIrqStatus — check RxDone vs Timeout vs CrcErr
6. GetRxBufferStatus [0x13, ...] — get length + start pointer
7. ReadBuffer(start, length) [0x1E, start, NOP, data...]
8. GetPacketStatus [0x14, ...] — get RSSI, SNR
9. ClearIrqStatus
10. Apply workaround 15.3 (stop RTC after Rx with timeout)